A multiplicity of active and passive electronic components which are electrically connected to one another according to a circuit construction of greater or lesser complexity are arranged on semiconductor circuits or integrated circuits (ICs) which are incorporated in many electronic devices. The components are formed in a semiconductor substrate and the integrated circuit is generally arranged in a housing equipped with terminal pins towards the outside in order to be able to produce an electrical connection to other external electrical circuits.
As the complexity of the integrated circuit arises, it is accompanied by a concomitant increase in the requirements made of the electronic components with regard to miniaturization, functional complexity and faster processing of information. It therefore becomes more and more difficult to design a complex integrated circuit comprising millions of transistors, inter alia, which are all clocked at a very high clock frequency. In a first step, a logical and functional design of such an integrated circuit is carried out, whereupon a logic network with logic gate cells is designed as a further step in order to implement the logically designed circuit therein. In this case, a logic gate cell is usually a relatively small unit comprising a plurality of transistors and other components that are combined in order to be able to carry out a specific logic operation. The resulting network constructed from the logic gate cells is described by a network list in which the corresponding logic gate cells and their electrical connections to one another are specified without a concrete physical circuit layout of the integrated circuit.
In order to create a physical circuit layout from the network list generated, so-called place & route software tools are used. Typical place & route software tools firstly place all the logic cells into a region in the center of the integrated circuit. By subsequently shifting the individual cells, the best possible positional placement of all the cells is carried out by means of the software, so-called filler cells and bypass capacitances between ground potential and supply voltage potential being arranged between the logic cells in order to be able to improve the performance and reliability of the integrated circuit. Afterwards, the corresponding wirings taken from the network list are formed in one or more planes in order to produce the electrical connections between the logic cells.
As already mentioned, during the automatic placement of the cells in accordance with the network list by means of place & route tools, gaps occasionally arise between the individual logic cells. So-called dummy logic blocks may be arranged in these gaps. One disadvantage of such dummy logic blocks that are inserted into an existing logic by means of a metal redesign also resides in the fact that these blocks have to be created and placed separately—independently of the logic—and require additional space without having a function. Furthermore, it is disadvantageous that only a specific cell repertoire is possible and relatively long wiring paths may arise.
The gaps that arise may also be filled with configurable gate array cells that are freely configurable by virtue of a metal redesign and thereby afford the possibility of carrying out an ECO fix (engineering change order=redesign owing to defective logic function) with a relatively low outlay. By means of such an ECO fix, the logic function of the gate array cell can be reprogrammed and integrated into the existing design.
One disadvantage of the known configurable gate array cells, however, is that the possibilities for the terminals of the poly gates constitute a considerable restriction. In general, these poly gate terminals are fitted between the doping regions at the transition from the p-conducting to the n-conducting doping zone. In order to connect a doping terminal to the poly gate of the adjacent cell, this has to be done transversely with respect to the preferred plane of the wiring, as a result of which, as it were, the so-called tracks (wiring tracks) are cut and the width of the wiring channel is reduced.
U.S. Pat. No. 5,923,060 discloses a configurable gate array cell containing one or more transistors. The doping zones of the transistors have an additional prong-shaped region which, in a plan view representation, extends in the vertical direction beyond the ends of the gate regions in order to enable electrical contact-connection to supply lines. The gate regions may extend in a preferred direction with a first part over the doping zones of a transistor. A gate terminal containing a second part extends perpendicularly to the preferred direction of the first part and adjoining the first part in lug-type fashion. The second part is formed such that, in a plan view representation of the gate array cell, it extends in the horizontal direction maximally as far as the limits of the doping zones. A disadvantage of this gate array cell is that the poly gate terminals enable only a relatively inadequate possibility of connection to adjacent gate array cells. The poly gate terminals extend in particular in the horizontal direction maximally as far as the dimensions of the doping zones, as a result of which the contact-connection to other gate array cells can be carried out in a relatively complicated and inadequate manner.